|
|
| 1 Purpose |
|
This document describes the unit testing of the SCHEMESTATION Virtual
Machine. The purpose of the unit testing is to show that the basic
functionality of the virtual machine functions is implemented and that
there are sufficient amount of checks for illegal instructions and
other malicious use of this unit - the testing should assure that there
are not direct possibilities to harm the VM from outside the module.
|
| 2 Test environment |
|
The unit tests do not require any particular environment apart from
the general SCHEMESTATION develoment environment (Development environment of the SchemeStation project: makefiles and related).
|
| 3 Instruction testing |
|
Each instruction function is tested separately. For each function the
following is tested:
- Illegal arguments (e.g. null pointers)
- Functionality (the instruction does what it it supposed to do)
The first two tests are actually carried out against the instruction
decoder, not the individual instruction functions. Overall, this testing
is much like black-box or grey-box testing, to be sure
that the external behaviour is well defined.
|
| 4 Other tests |
|
The VM unit interface is tested as follows:
- Each interface function is called with illegal arguments
- Basic functionality of the interface functions is tested
Besides public unit interface, there are interfaces for
instruction encoding and decoding; all these functions are
cross-checked so that encodings and decodings correspond
each other.
For further information not present here, see the actual test file.
|
| 5 Test cases |
|
All test cases for the virtual machine can be found in the
schemestation source distribution, from file
./src/libsrc/vm/vm_tester.c, except make_instruction(), which
is tested in the file ./src/libsrc/vm/mkinstr.c.
|
| 5.1 Instruction decoders |
|
All instruction decoders are tested with the following criteria:
- Try to decode invalid instructions (e.g. register specifier out of range)
- Check that the registers are decoded correctly
- Enforce the checking of the constants used
Test cases (first part: (D)one, (U)ndone, (I)ncomplete,
second part: (S)uccess, (U)nsuccess, (I)ncomplete):
| # | Decoder | Invalid arguments | Functionality |
| 1 | decoder_reg1 | D/S | D/S |
| 2 | decoder_reg1const | D/S | D/S |
| 3 | decoder_reg12 | D/S | D/S |
| 4 | decoder_reg12const | D/S | D/S |
| 5 | decoder_reg123 | D/S | D/S |
| 6 | decoder_reg1234 | D/S | D/S |
| 7 | decoder_nop | D/S | D/S |
| 8 | make_instruction | D/S | D/S |
| | Done | | 8 | 8 |
| | Success | | 8 | 8 |
| | Total result | | 100% | 100% |
|
| 5.2 Instructions (and exceptions) |
|
For each instruction, there are tests for the basic functionality
of the instruction (semantics). In addition, possible invalid
arguments are monitored.
Test cases (first part: (D)one, (U)ndone, (I)ncomplete,
second part: (S)uccess, (U)nsuccess, (I)ncomplete):
| # | Instruction | Arguments | Invalid arguments | Functionality |
| 0 | NOP | | D/S | D/S |
| 1 | HALT | | D/S | D/S |
| 2 | JUMP | REG | D/S | D/S |
| 3 | JUMP_IMMEDIATE | LABEL | D/S | D/S |
| 4 | BRANCH | REG REG | D/S | D/S |
| 5 | BRANCH_IMMEDIATE | REG LABEL | D/S | D/S |
| 6 | PUSH | REG REG | D/S | D/S |
| 7 | POP | REG REG | D/S | D/S |
| 8 | SET_EXCEPTION_HANDLER | REG | D/S | D/S |
| 11 | SEND_MESSAGE | REG REG | D/S | D/S |
| 14 | CREATE_PROCEDURE | REG REG REG | D/S | D/S |
| 15 | GET_PROCEDURE_ENV | REG REG | D/S | D/S |
| 16 | GET_PROCEDURE_ADDRESS | REG REG | D/S | D/S |
| 17 | IS_OF_BOOLEAN | REG REG | D/S | D/S |
| 18 | IS_OF_INTEGER | REG REG | D/S | D/S |
| 19 | IS_OF_FLOAT | REG REG | D/S | D/S |
| 20 | IS_OF_PAIR | REG REG | D/S | D/S |
| 21 | IS_OF_PAIR_TAGGED | REG REG REG | D/S | D/S |
| 22 | IS_OF_VECTOR | REG REG | D/S | D/S |
| 23 | IS_OF_VECTOR_TAGGED | REG REG REG | D/S | D/S |
| 24 | IS_OF_PRIVATE_BIT_STRING | REG REG | D/S | D/S |
| 25 | IS_OF_PRIVATE_BIT_STRING_TAGGED | REG REG REG | D/S | D/S |
| 26 | IS_OF_SHARED_BIT_STRING | REG REG | D/S | D/S |
| 27 | IS_OF_SHARED_BIT_STRING_TAGGED | REG REG REG | D/S | D/S |
| 28 | IS_OF_PROCEDURE | REG REG | D/S | D/S |
| 31 | MOVE | REG REG | D/S | D/S |
| 32 | LOAD | REG LITERAL | D/S | D/S |
| 33 | LOAD_NULL | REG | D/S | D/S |
| 34 | INT_ADD | REG REG REG | D/S | D/S |
| 35 | INT_SUB | REG REG REG | D/S | D/S |
| 36 | INT_MUL | REG REG REG | D/S | D/S |
| 37 | INT_DIV | REG REG REG | D/S | D/S |
| 38 | INT_MOD | REG REG REG | D/S | D/S |
| 39 | INT_REM | REG REG REG | D/S | D/S |
| 40 | FLOAT_ADD | REG REG REG | D/S | D/S |
| 41 | FLOAT_SUB | REG REG REG | D/S | D/S |
| 42 | FLOAT_MUL | REG REG REG | D/S | D/S |
| 43 | FLOAT_DIV | REG REG REG | D/S | D/S |
| 44 | FLOAT_MOD | REG REG REG | D/S | D/S |
| 45 | FLOAT_REM | REG REG REG | D/S | D/S |
| 46 | FLOAT_LOG | REG REG | D/S | D/S |
| 47 | FLOAT_LOG10 | REG REG | D/S | D/S |
| 48 | FLOAT_EXP | REG REG | D/S | D/S |
| 49 | FLOAT_SQRT | REG REG | D/S | D/S |
| 50 | SHR | REG REG REG | D/S | D/S |
| 51 | SHL | REG REG REG | D/S | D/S |
| 52 | AND | REG REG REG | D/S | D/S |
| 53 | OR | REG REG REG | D/S | D/S |
| 54 | XOR | REG REG REG | D/S | D/S |
| 55 | NEG | REG REG | D/S | D/S |
| 56 | ROR | REG REG REG | D/S | D/S |
| 57 | ROL | REG REG REG | D/S | D/S |
| 58 | LAND | REG REG REG | D/S | D/S |
| 59 | LOR | REG REG REG | D/S | D/S |
| 60 | NOT | REG REG | D/S | D/S |
| 61 | BOOLEAN_NOT | REG REG | D/S | D/S |
| 62 | INT_TO_FLOAT | REG REG | D/S | D/S |
| 63 | FLOAT_TO_INT | REG REG | D/S | D/S |
| 64 | INT_TO_BIT_STRING | REG REG REG | D/S | D/S |
| 65 | BIT_STRING_TO_INT | REG REG REG | D/S | D/S |
| 66 | EQ | REG REG REG | D/S | D/S |
| 67 | INT_CMP | REG REG REG | D/S | D/S |
| 68 | FLOAT_CMP | REG REG REG | D/S | D/S |
| 69 | INT_GE | REG REG REG | D/S | D/S |
| 70 | FLOAT_GE | REG REG REG | D/S | D/S |
| 71 | GET_SUBSTRING | REG REG REG REG | D/S | D/S |
| 72 | SET_SUBSTRING | REG REG REG | D/S | D/S |
| 73 | ALLOC_PAIR | REG | D/S | D/S |
| 74 | ALLOC_PAIR_TAGGED | REG REG | D/S | D/S |
| 75 | ALLOC_VECTOR | REG REG | D/S | D/S |
| 76 | ALLOC_VECTOR_TAGGED | REG REG REG | D/S | D/S |
| 77 | ALLOC_SHARED_BIT_STRING | REG REG | D/S | D/S |
| 78 | ALLOC_SHARED_BIT_STRING_TAGGED | REG REG REG | D/S | D/S |
| 79 | ALLOC_PRIVATE_BIT_STRING | REG REG | D/S | D/S |
| 80 | ALLOC_PRIVATE_BIT_STRING_TAGGED | REG REG REG | D/S | D/S |
| 81 | PAIR_SET_CAR | REG REG | D/S | D/S |
| 82 | PAIR_SET_CDR | REG REG | D/S | D/S |
| 83 | PAIR_GET_CAR | REG REG | D/S | D/S |
| 84 | PAIR_GET_CDR | REG REG | D/S | D/S |
| 85 | VECTOR_SET | REG REG REG | D/S | D/S |
| 86 | VECTOR_GET | REG REG REG | D/S | D/S |
| 87 | VECTOR_SET_INDEX | REG REG LITERAL | D/S | D/S |
| 88 | VECTOR_GET_INDEX | REG REG LITERAL | D/S | D/S |
| 89 | VECTOR_LEN | REG REG | D/S | D/S |
| 90 | BIT_STRING_LEN | REG REG | D/S | D/S |
| 91 | COPY_PAIR | REG REG | D/S | D/S |
| 92 | COPY_VECTOR | REG REG | D/S | D/S |
| 93 | COPY_BIT_STRING | REG REG | D/S | D/S |
| 94 | CONS | REG REG REG | D/S | D/S |
| 95 | SAVE | REG REG | D/S | D/S |
| 96 | RESTORE | REG REG | D/S | D/S |
| 97 | ALLOC_INTEGER | REG | D/S | D/S |
| 98 | ALLOC_FLOAT | REG | D/S | D/S |
| 99 | ALLOC_BOOLEAN | REG | D/S | D/S |
| 100 | INTEGER_SET | REG REG | D/S | D/S |
| 101 | FLOAT_SET | REG REG | D/S | D/S |
| 102 | BOOLEAN_SET | REG REG | D/S | D/S |
| 103 | INTEGER_GET | REG REG | D/S | D/S |
| 104 | FLOAT_GET | REG REG | D/S | D/S |
| 105 | BOOLEAN_GET | REG REG | D/S | D/S |
| 106 | PAIR_GET_CAR_OR_BLOCK | REG REG | D/S | D/S |
| 107 | ALLOC_VECTOR_IMMEDIATE | REG LITERAL | D/S | D/S |
| 108 | CREATE_PROCEDURE_IMMEDIATE | REG REG LABEL | D/S | D/S |
| 109 | SAVE_IMMEDIATE | REG LITERAL | D/S | D/S |
| 110 | RESTORE_IMMEDIATE | REG LITERAL | D/S | D/S |
| 111 | BIT_STRING_CMP | REG REG REG | D/S | D/S |
| 112 | BIT_STRING_GE | REG REG REG | D/S | D/S |
| 113 | TAG_CMP | REG REG LITERAL | D/S | D/S |
| 114 | IMM_EXTEND | [special] | D/S | D/S |
| | Done | | 110 | 110 |
| | Undone | | 0 | 0 |
| | Incomplete | | 0 | 0 |
| | Success | | 110 | 110 |
| | Unsuccess | | 0 | 0 |
| | Incomplete | | 0 | 0 |
| | Total result | | 100% | 100% |
|
| 5.3 Messages |
|
The message delivery and reception is verified separately. The incoming
message handling has to block any further messages until the current
message has been handled. The message testing is implicitly part of
both the integration and the system testing.
|
| 5.4 VM Unit Interface |
|
SCHEMESTATION Virtual Machine Unit Interface consists of the
following functions:
vm_execute()
vm_message()
make_instruction()
reverse_map_instruction()
All these functions are tested with illegal parameters.
The actual testing of this interface is carried out in the
integration testing (except make_instruction(), which
is tested in the file ./src/libsrc/vm/mkinstr.c),
due to the fact that they represent the functionality
and semantics of the whole SSVM unit.
|